The reset system includes resets generated by hardware, watchdog timers, the JTAG controller, and software. Every module and system in Zynq-7000 AP SoC devices includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B). The user can reset the entire system by asserting a software reset. By asserting PSS_RST_CTRL[SOFT_RST], the entire system is reset with the same end result as the user pressing the PS_SRST_B pin (other than the REBOOT_STATUS register value being different). Just like the other system resets, all of the RAMs are cleared and the PL is reset as well. Related register : SLCR_LOCK Relative Address : 0x00000004 Absolute Address : 0xF8000004 Width : 32 bits Access Type : wo Reset Value : 0x00000000 Description : SLCR Write Protection Lock SLCR_UNLOCK Relative Address : 0x00000008 Absolute Address : 0xF8000008 Width : 32 bits Access Type...