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error: ***.elf uses VFP register arguments, ***.o does not

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Xilinx Application Note : xapp1206 將-mfpu= vfpv3  -mfloat-abi= hard (default)設定成 -mfpu= neon  -mfloat-abi= softfp 會出現下列錯誤訊息 solution: step1: C/C++ Build -> Settings -> Tool Settings ARM v7 gcc compiler -> Miscellaneous Linker Flags : -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu= neon -mfloat-abi= softfp ARM v7 gcc linker -> Miscellaneous Linker Flags : -mcpu=cortex-a9 -mfpu= neon -mfloat-abi= softfp -Wl,-build-id=none -specs=Xilinx.spec step2 :  Modify this BSP’s Settings -> Overview -> Drivers -> ps7_cortexa9_0 Extra_compiler_flags : -mcpu=cortex-a9 -mfpu= neon -mfloat-abi= softfp -nostartfiles -Wall -Wextra

Call sin, cos tan functions in Xilinx SDK

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Solution The math "m" option needs to be specified in the Libraries in the C/C++ Build Settings. ref : https://www.xilinx.com/support/answers/52971.html

Zynq-7000 AP SoC by software reset

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The reset system includes resets generated by hardware, watchdog timers, the JTAG controller, and software. Every module and system in Zynq-7000 AP SoC devices includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B). The user can reset the entire system by asserting a software reset. By asserting PSS_RST_CTRL[SOFT_RST], the entire system is reset with the same end result as the user pressing the PS_SRST_B pin (other than the REBOOT_STATUS register value being different). Just like the other system resets, all of the RAMs are cleared and the PL is reset as well. Related register : SLCR_LOCK Relative Address : 0x00000004 Absolute Address : 0xF8000004 Width : 32 bits Access Type : wo Reset Value : 0x00000000 Description : SLCR Write Protection Lock SLCR_UNLOCK Relative Address : 0x00000008 Absolute Address : 0xF8000008 Width : 32 bits Access Type...